3D packaging concerns system on chip (SOC) and system in package (SIP) configurations. TSV 3D packages may contain two or more chips stacked vertically, with vias through silicon substrates replacing edge wiring to create an electrical connection between the circuit elements on each chip.
Standards, such as the Joint Electron Devices Engineering Council's (JEDEC) JEDEC “Design Registration-Micropillar Grid Array (MPGA)”, DR-4.26A, December 2011, Item 11.2-845(R), define the chip-to-chip landing pad interface for a logic-to-memory interface. Conventionally, the physical locations of TSVs are located directly beneath the landing pad locations on a chip, which takes up a great deal of die area. This means that all other circuitry is laid out around the TSV locations.
During TSV processing, the array of TSVs are formed through a thinned device wafer. Conventional TSV structures use either silicon dioxide or polymers as an insulator material on the backside of the thinned device wafer. These materials are not hermetic, and do not provide a robust passivation layer on the backside of the thinned device wafer.